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VOXL Connectors

Table of contents

  1. Board Connections and Pin-out Specifications
    1. VOXL Board Top
    2. VOXL Board Bottom
    3. Connector Pin-outs and Specifications
      1. J1 5V DC IN, I2C to power cable “APM”
      2. J2 4k Camera (CSI0)
        1. Supported Cameras
      3. J3 Stereo or Time-of-flight Camera (CSI1)
        1. Supported Cameras
      4. J4 Tracking/Optic Flow Camera (CSI2)
        1. Supported Cameras
      5. J6 Cooling Fan Connector
      6. J7 BLSP6 (I2C + GPIO) and BLSP9 (UART / SPI): External GPS/MAG
      7. J8 USB 3.0 OTG
      8. J9 Micro-SD Slot
      9. J10 UART or I2C off-board (external Sonar or IMU sensor)
      10. J11 BLSP12 off-board (SPEKTRUM)
      11. J12 BLSP5 off-board (UART ESC)
      12. J13 Expansion B2B connection
      13. J14 Integrated GNSS Antenna Connection
      14. Wi-Fi Antenna Connectors (2)
        1. Supported Antennas
      15. RGB LED
  2. Expansion Board Details

Board Connections and Pin-out Specifications

VOXL Board Top

VOXL Core Top

ConnectorSummary 
J2Hires 4k Image Sensor (CSI0)Details
J3Stereo Image Sensor (CSI1)Details
J6Cooling Fan ConnectorDetails
J7BLSP6 (GPIO) and BLSP9 (UART): External GPS/MAGDetails
J13Expansion B2BDetails
J14Integrated GNSS Antenna ConnectionDetails

VOXL Board Bottom

VOXL Core Top

ConnectorSummary 
J15V DC IN, I2C to power cable “APM”Details
J4Tracking/Optic Flow Image Sensor (CSI2)Details
J8USB 3.0 OTGDetails
J9Micro-SD SlotDetails
J10BLSP7 UART and I2C off-boardDetails
J11BLSP12 UART and I2C off-board (SPEKTRUM)Details
J12BLSP5 UART and GPIO off-board (ESC)Details
Wi-FiExternal Wi-Fi antenna connectionsDetails

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Connector Pin-outs and Specifications

J1 5V DC IN, I2C to power cable “APM”

Pin Configuration
Pin #Signal NameAlt Function
15V DC 
2GND 
3I2C8_SCLGPIO 7
4I2C8_SDAGPIO 6
Connector
Mating Connector
  • 50-37-5043 based cables
Notes
  • I2C8 is at 5V CMOS with 10K pull-ups.
  • Connect to provided power cable for proper operation and current handling.

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J2 4k Camera (CSI0)

J2 Board ConnectorCamera (Flex) Mating Connector
Panasonic, MPN: AXT336124Panasonic MPN: AXT436124

Pin-out:

Pin #Signal NamePin #Signal Name
1GND2GND
3VREG_L17A_2P8 (AFVDD)4CAM0_STANDBY_N
5CCI_I2C_SDA06VREG_LVS1A_1P8 (DOVDD)
7CCI_I2C_SCL08VREG_L3A_1P1 (DVDD)
9CAM0_RST0_N10CAM_MCLK0_BUFF
11GND12GND
13MIPI_CSI0_CLK_CONN_P14CAM_FLASH
15MIPI_CSI0_CLK_CONN_M16CAM_SYNC_0
17MIPI_CSI0_LANE0_CONN_P18CAM0_MCLK3
19MIPI_CSI0_LANE0_CONN_M20VREG_L22A_2P8 (AVDD)
21GND22GND
23MIPI_CSI0_LANE1_CONN_P24CAM_RST1_N
25MIPI_CSI0_LANE1_CONN_M26CAM_SYNC_1
27MIPI_CSI0_LANE2_CONN_P28CCI_I2C_SDA1
29MIPI_CSI0_LANE2_CONN_M30CCI_I2C_SCL1
31GND32GND
33MIPI_CSI0_LANE3_CONN_P34VPH_PWR
35MIPI_CSI0_LANE3_CONN_M36GND
Supported Cameras

The following sensors are supported on J2 (CSI0):

  • IMX214
  • IMX230
  • IMX377
  • IMX378
  • OV16825

Supported modules:

DescriptionMPNLinkDatasheet
ModalAI Sony IMX214 wide angleMCAM-00024BuyDatasheet
ModalAI Sony IMX214MCAM-00024BuyDatasheet
ModalAI Sony IMX377MCAM-00026BuyDatasheet

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J3 Stereo or Time-of-flight Camera (CSI1)

J3 Board ConnectorCamera (Flex) Mating Connector
Panasonic MPN: AXT336124Panasonic MPN: AXT436124

Pin-out:

Pin #Signal NamePin #Signal Name
1GND2GND
3VREG_L18A_2P8 (AFVDD)4CAM1_STANDBY_N
5CCI_I2C_SDA06VREG_S4A_1P8 (DOVDD)
7CCI_I2C_SCL08VREG_L3A_1P1 (DVDD)
9CAM1_RST0_N10CAM_MCLK1_BUFF
11GND12GND
13MIPI_CSI1_CLK_CONN_P14CAM_FLASH
15MIPI_CSI1_CLK_CONN_M16CAM_SYNC_0
17MIPI_CSI1_LANE0_CONN_P18CAM1_MCLK3
19MIPI_CSI1_LANE0_CONN_M20VREG_L23A_2P8 (AVDD)
21GND22GND
23MIPI_CSI1_LANE1_CONN_P24CAM_RST1_N
25MIPI_CSI1_LANE1_CONN_M26CAM_SYNC_1
27MIPI_CSI1_LANE2_CONN_P28CCI_I2C_SDA1
29MIPI_CSI1_LANE2_CONN_M30CCI_I2C_SCL1
31GND32GND
33MIPI_CSI1_LANE3_CONN_P34VPH_PWR
35MIPI_CSI1_LANE3_CONN_M36GND
Supported Cameras

The following sensors are supported on J3 (CSI1):

Supported modules:

DescriptionMPNLinkDatasheet
Stereo Camera Pair for Obstacle Avoidance KitMKIT-00009BuyDatasheet
PMD Time of FlightMKIT-00017-3BuyDatasheet

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J4 Tracking/Optic Flow Camera (CSI2)

J4 Board ConnectorCamera (Flex) Mating Connector
Panasonic, MPN: AXT336124Panasonic MPN: AXT436124

Pin-out:

Pin #Signal NamePin #Signal Name
1GND2GND
3VREG_L29A_2P8 (AFVDD)4CAM2_STANDBY_N
5CCI_I2C_SDA06VREG_LVS1A_1P8 (DOVDD)
7CCI_I2C_SCL08VREG_L3A_1P1 (DVDD)
9CAM2_RST0_N10CAM_MCLK2_BUFF
11GND12GND
13MIPI_CSI2_CLK_CONN_P14CAM_FLASH
15MIPI_CSI2_CLK_CONN_M16CAM_SYNC_0
17MIPI_CSI2_LANE0_CONN_P18CAM2_MCLK3
19MIPI_CSI2_LANE0_CONN_M20VREG_L23A_2P8 (AVDD)
21GND22GND
23MIPI_CSI2_LANE1_CONN_P24CAM_RST1_N
25MIPI_CSI2_LANE1_CONN_M26CAM_SYNC_1
27MIPI_CSI2_LANE2_CONN_P28CCI_I2C_SDA1
29MIPI_CSI2_LANE2_CONN_M30CCI_I2C_SCL1
31GND32GND
33MIPI_CSI2_LANE3_CONN_P34VPH_PWR
35MIPI_CSI2_LANE3_CONN_M36GND
Supported Cameras

The following sensors are supported on J4 (CSI2):

Supported modules:

DescriptionMPNLinkDatasheet
Sunny MD102A w/ FPC-M0008 Rev A AdapterMKIT-00010Buy 
ModalAI 166-degree OV7251 B&W VGA Global ShutterMCAM-00014MKIT-00010-2 Coming Soon 

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J6 Cooling Fan Connector

Pin Configuration
Pin #Signal Name
1EXT_FAN_5V
2EXT_FAN_RET
Connector
Mating Connector

VOXL Side:

Fan Side:

Notes

Supported Fan Module:

  • DDH Enterprise, Inc, MPN: DDH-2016-013 MCN: 420-59855-0001

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J7 BLSP6 (I2C + GPIO) and BLSP9 (UART / SPI): External GPS/MAG

Pin Configuration
Pin #Signal NameAlt Function
1VREG_3P3V 
2BLSP9_UART_TX_3P3GPIO 49 / BLSP9_SPI_MOSI
3BLSP9_UART_RX_3P3GPIO 50 / BLSP9_SPI_MISO
4BLSP6_I2C_SDA_3P3GPIO 27
5GND 
6BLSP6_I2C_SCL_3P3GPIO 28
7BLSP6_GPIO_26_AUX2_3P3GPIO 26
8BLSP6_GPIO_25_AUX1_3P3GPIO 25
9BLSP9_UART_CTS_N_3P3GPIO 51 / BLSP9_SPI_CS_N
10BLSP9_UART_RFR_N_3P3GPIO 52 / BLSP9_SPI_CLK
Connector
Mating Connector

VOXL Side:

GPS/MAG Side:

Notes

Supported GPS Module:

The above uses antenna:

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J8 USB 3.0 OTG

Pin Configuration
Pin #Signal Name
1VBUS
2D-
3D+
4ID
5GND
6MICA_SSTX-
7MICA_SSTX+
8GND_DRAIN
9MICA_SSRX-
10MICA_SSRX+
Connector
Mating Connector
  • Micro A/B Plug
Notes
  • Host mode USB 3.0 (e.g. connect a supported USB 3.0 device) requires Micro-A Plug to STD-A in order to get 3.0 SS Functionality. Example cable: Amphenol RUB30-0075 (contact ModalAI for details, available as MCBL-00019)
  • Host mode USB 2.0 - example cable

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J9 Micro-SD Slot

Pin Configuration
Pin #Signal Name
1DAT2
2CD/DAT3
3CMD
4VDD
5CLK
6VSS (GND)
7DAT0
8DAT1
Connector
Mating Connector
  • Micro-SD Cards

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J10 UART or I2C off-board (external Sonar or IMU sensor)

Pin Configuration
Pin #Signal NameAlt Function
1VREG_3P3V 
2SONAR_UART_TX_3P3GPIO 53
3SONAR_UART_RX_3P3GPIO 54
4EXT_IMU_I2C_SDA_3P3GPIO 55
5GND 
6EXT_IMU_I2C_SCL_3P3GPIO 56
Connector
Mating Connector
  • DF13-6S-1.25C cable assemblies
Notes
  • UART and I2C are at 3.3V CMOS levels.
  • Connect TX to target device’s RX, and vice-versa.
  • I2C has 10K pull-ups.

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J11 BLSP12 off-board (SPEKTRUM)

Pin Configuration
Pin #Signal NameAlt Function
1VREG_3P3V_SPEKTRUM 
2BLSP12_UART_TX_3P3GPIO 85
3BLSP12_UART_RX_3P3GPIO 86
4BLSP12_I2C_SDA_3P3GPIO 87
5GND 
6BLSP12_I2C_SCL_3P3GPIO 88
Connector
Mating Connector
  • DF13-6S-1.25C cable assemblies
Notes
  • UART and I2C are at 3.3V CMOS levels.
  • Connect TX to target device’s RX, and vice-versa.
  • I2C has 10K pull-ups.

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J12 BLSP5 off-board (UART ESC)

Pin Configuration
Pin #Signal NameAlt Function
1VDCIN_5V 
2ESC_UART_TX_5VGPIO 81
3ESC_UART_RX_5VGPIO 82
4BLSP5_GPIO_83_5VGPIO 83
5GND 
6BLSP5_GPIO_84_5VGPIO 84
Connector
Mating Connector
  • DF13-6S-1.25C cable assemblies
Notes
  • UART and GPIOs are at 5V CMOS levels
  • Connect TX to target device’s RX, and vice-versa.
  • GPIO’s are not set for I2C (no pull-ups, push-pull driver).

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J13 Expansion B2B connection

Pin Configuration
Pin #Signal NamePin #Signal Name
1GND2VDCIN_5V_CONN
3APQ_GPIO_964VDCIN_5V_CONN
5APQ_GPIO_956VDCIN_5V_CONN
7APQ_GPIO_948USB2_HS_ID
9APQ_GPIO_9210GND
11GND12USB2_HS_D_M
13BLSP11_0_SCL_GPIO6114USB2_HS_D_P
15BLSP11_1_SDA_GPIO6016USB2_HS_VBUS_CONN
17BLSP11_2_RX_GPIO5918GND
19BLSP11_3_TX_GPIO5820APQ_GPIO_64
21GND22APQ_GPIO_127
23BLSP8_0_SCL_GPIO724APQ_GPIO_126
25BLSP8_1_SDA_GPIO626APQ_GPIO_70
27BLSP8_2_RX_GPIO528APQ_GPIO_71
29BLSP8_3_TX_GPIO430APQ_GPIO_72
31GND32APQ_GPIO_93
33JTAG_TDO34APQ_GPIO_91
35JTAG_SRST_N36GND
37JTAG_TCK38APQ_GPIO_106
39JTAG_TDI40APQ_GPIO_107
41JTAG_TMS42APQ_GPIO_108
43JTAG_TRST_N44GND
45JTAG_PS_HOLD46APQ_GPIO_114
47VREG_S4A_1P848APQ_GPIO_104
49PMIC_RESIN_N50APQ_GPIO_103
51APQ_RESOUT_N52APQ_GPIO_102
53VREG_3P3V54APQ_GPIO_101
55KYPDPWR_N56APQ_GPIO_57
57VPH_PWR58GND
59GND60PM8996_GPIOC15
Connector
Mating Connector

VOXL Side:

Debug Board Side:

Notes

Supported Debug B2B Module:

  • Eagle Nest, MCN: 20-H9420-1
  • Serial Feather PRO Edition, MCN: 30-H9916-1

More details are available here.

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J14 Integrated GNSS Antenna Connection

Pin Configuration
  • Center Conductor
Connector
Mating Connector

VOXL Side:

GNSS Antenna Side:

Notes

Supported Module:

  • CABLE ASSY, U.FL TO SMA-F BHD, 1.32 MM COAX MCN: CV90-N5175-A4
  • Passive antenna configuration (no DC bias)

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Wi-Fi Antenna Connectors (2)

Function
  • External Wi-Fi antenna connections
Pin Configuration
  • Center Conductor
Connector
Mating Connector
Supported Antennas
Notes
  • ANT #1 is for WLAN/BT
  • ANT #2 is for WLAN only

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RGB LED

Function
  • Fixed functionality, momentarily flashes green on normal system boot up

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Expansion Board Details

The following apply to the expansion board connector J13.

Voltage

Independently, each power rail can provide 1A to circuitry on the B2B mating designs, however, the total current consumed by all power rails should not exceed 1.5A as this ultimately impacts VDCIN_5V_CONN. The signals are listed here:

SignalDescription and Use
GNDMain board ground (DC 0V and signal return path).
VDCIN_5V_CONNThis is the same 5V that is present on the Excelsior Flight controller board input power connector (J14) when powered by the provided 5V DC power supply and the APM board. This is primarily used to provide power up to circuitry on the expansion connector’s mating board, up to 1A.
VPH_PWRMain power node input of all the on-board PMIC regulators. This is in the range of 4.15V to 4.25V nominally. This can be used to provide power up to circuitry on the expansion connector’s mating board, up to 1A.
VREG_3P3VPrimary 3.3V on the main board. This can be used to provide power up to circuitry on the expansion connector’s mating board, up to 1A. This is useful for voltage translators for the many 1.8V signals.
VREG_S4A_1P8Primary 1.8V I/O rail on the main board. This can be used to provide power up to circuitry on the expansion connector’s mating board, up to 1A. This is useful for voltage translators for the many 1.8V signals.
USB2_HS_VBUS_CONNUSB Port 2 host power. The main board provides a 500mA power switch from VDCIN_5V to provide host-mode support to USB 2.0 peripherals. This is most commonly used to provide the 5V to a USB2.0 HOST connector (Type A) on any mating circuit board.

USB 2.0

A standard USB 2.0 host port is available on the debug connector. A peripheral can be hard-wired to this port (hub or WLAN application) or a USB compliant Type-A connector can be made available on any mating design for other peripheral types. The signals are listed here:

SignalDescription and Use
USB2_HS_VBUS_CONNUSB Port 2 host power. The main board provides a 500mA power switch from VDCIN_5V to provide host-mode support to USB 2.0 peripherals.
USB2_HS_D_PUSB high-speed 2 data – plus
USB2_HS_D_MUSB high-speed 2 data – minus
USB2_HS_IDUSB-OTG ID pin. This signal is grounded on the main board through a 0- ohm resistor. This is provided only for the application where a Type-A/B (OTG) connector is provided and the ID pin is required to identify the port as a HOST.

BLSP Signals

Three complete BLSP ports are available on the debug connector. Software has the ability to configure these ports as a 4-wire UART, 2-wire UART + I2C, I2C + 2 GPIO, SPI, or as four GPIOs. All signals are 1.8V CMOS, and when configured as digital outputs, the drive strength can be set between 2mA – 16mA in 2mA steps. The signals are listed here:

It is advised not to change the configuration of BLSP8 2-wire UART as this is configured as the debug console by default.

SignalDescription and Use
BLSP11_0_SCL_GPIO61BLSP port 11, bit 0. RFR when configured for 4-wire UART, SCL when configured as I2C, SPI_CLK when configured as SPI, or GPIO84 when set as GPIO.
BLSP11_1_SDA_GPIO60BLSP port 11, bit 1. CTS when configured for 4-wire UART, SDA when configured as I2C, SPI_CS_N when configured as SPI, or GPIO83 when set as GPIO.
BLSP11_2_RX_GPIO59BLSP port 11, bit 2. UART_RX (input) when configured as UART, SPI_MISO when configured as SPI, or GPIO82 when set as GPIO.
BLSP11_3_TX_GPIO58BLSP port 11, bit 3. UART_TX (output) when configured as UART, SPI_MOSI when configured as SPI, or GPIO81 when set as GPIO.
BLSP8_0_SCL_GPIO7BLSP port 12, bit 0. RFR when configured for 4-wire UART, SCL when configured as I2C, SPI_CLK when configured as SPI, or GPIO88 when set as GPIO.
BLSP8_1_SDA_GPIO6BLSP port 12, bit 1. CTS when configured for 4-wire UART, SDA when configured as I2C, SPI_CS_N when configured as SPI, or GPIO87 when set as GPIO.
BLSP8_2_RX_GPIO5BLSP port 12, bit 2. UART_RX (input) when configured as UART, SPI_MISO when configured as SPI, or GPIO86 when set as GPIO. Note: This is the default debug serial console RX pin
BLSP8_3_TX_GPIO4BLSP port 12, bit 3. UART_TX (output) when configured as UART, SPI_MOSI when configured as SPI, or GPIO85 when set as GPIO. Note: This is the default debug serial console TX pin.

Configuration and JTAG Signals

Several configuration and JTAG signals are available on the debug connector. These signals are critical to proper boot-up and system operation, and as such, the end user is advised to not use these signals in any capacity unless they are very securely aware of the boot modes and processes of the VOXL chipset architecture, or with JTAG. Failure to do so could result in a bricked board. The signals are here:

SignalDescription and Use
APQ_GPIO_114Advised to ignore signal on any external mating designs.
APQ_GPIO_104Advised to ignore signal on any external mating designs.
APQ_GPIO_103Advised to ignore signal on any external mating designs.
APQ_GPIO_102Advised to ignore signal on any external mating designs.
APQ_GPIO_101Watchdog disable boot control. Connect to VREG_S3A via 10k-Ohm resistor to disable the watchdog.
APQ_GPIO_57FORCE_USB_BOOT signal. Connect to VREG_S3A via 10k-Ohm resistor to have the boot loader ignore the programmed image and enter “QDOWNLOAD Mode” to re-image a bricked board. Remove pull-up connection when completed.
JTAG_SRST_NAdvised to ignore signal on any external mating designs.
JTAG_TCKAdvised to ignore signal on any external mating designs.
JTAG_TDIAdvised to ignore signal on any external mating designs.
JTAG_TDOAdvised to ignore signal on any external mating designs.
JTAG_TMSAdvised to ignore signal on any external mating designs.
JTAG_TRST_NAdvised to ignore signal on any external mating designs.
JTAG_PS_HOLDAdvised to ignore signal on any external mating designs.
PMIC_RESIN_NPMIC GPIO2 for Reset. Advised to ignore signal on any external mating designs.
APQ_RESOUT_NAdvised to ignore signal on any external mating designs.
KYPDPWR_NAdvised to ignore signal on any external mating designs.

Using Configuration GPIOs

As mentioned above, several APQ_GPIOs are reserved for configuration purposes and advised to ignore. However, if these signals must be used, there is a way to utilize them with some added isolation circuitry.

Upon boot up, the applications processor is brought into the correct mode by settings on the Excelsior Flight main board. This boot mode is determined by pin strapping of the boot mode signals upon reset; GPIO_103, and GPIO_[112:116]. After reset, these signals can be reclaimed for general purpose, but it is imperative to keep them tri-stated prior to reset to not interfere with the settings on the Excelsior Flight main board or the applications processor can fail to boot, or boot into an unknown state.

The most effective way to reclaim these signals is to use a bidirectional signal translator with auto-direction sensing and signal isolation with an active high enable pin. This will allow the user to not only voltage translate to the desired level they need, but also allows for either direction usage.

An example schematic of how this can be achieved is shown here:

VOXL Core Top

If the exact circuit is not followed, here are the key things to note:

  • The translator MUST tri-state the PORT_1 side I/O’s if either VCC_PORT_1 or OE is LOW/GND.
  • APQ_RESOUT_N going HIGH is the indicator of when the signals are no longer being sampled for boot mode configuration.
  • Be sure the translator can accept 1.8V on VCC_PORT_1, and OE input is referenced to VCC_PORT_1.
  • If the direction is known ahead of time, other devices can be used to achieve the desired purpose, such as discrete FETs, but ensure they are logic-level and can operate at VGS of 1V-1.8V.
  • DO NOT place any shunt resistors, capacitors, or other circuit elements in-between the GPIOs from the debug connector to the isolation circuits.
    • ESD protection is already provided on the Excelsior Flight main board.

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